Digital computing system



Jan. 9, 1962 L. s. BENSKY Erm. 3,016,194

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Jan. 9,1962 L. s. BENsKY ErAL 3,016,194

DIGITAL COMPUTING SYSTEM Filed Nov. I, 1955 e sheets-sheet 4 Jan. 9,1962 l.. s. BENSKY Erm. 3,016,194

DIGITAL COMPUTING SYSTEM Filed Nov. 1, 1955 8 Sheets-Sheet 5 Jan. 9,1962 l.. s. BENsKY l-:TAL 3,016,194

DIGITAL COMPUTING SYSTEM 8 Sheets-Sheet 6 Filed. Nov. l, 1955 I ATTORNEYJan. 9, 1962 L.. s. BENsKY ETAL DIGITAL COMPUTING SYSTEM 8 Sheets-Sheet'I Filed. Nov. l, 1955 UNL hunk ha MTM TINT H m bum hw #IRWIN mwN IN VENTORS. J enaky Mzlewz d Via? BY rivm/Ex Jan. 9, 1962 l.. s. Br-:NsKY ETAL3,016,194

DIGITAL COMPUTING SYSTEM Filed Nov. l, 1955 8 Sheets-Sheet 8 A HE G. CH56.

United States Patent O 3,016,194 DEGK'EAL COMPUTHNG SYSTEM Lowell S.Beasley, Levittown, Pa., and David L. Nettleton, Haddoneld, NJ.,assignors to Radio Corporation of America, .a corporation of DelawareFiied Nov. 1, 1955. Ser. No.. 544,275 23 Claims. (Cl. 23S-157) DIGITALCOMPUTING SYSTEM Table of contents 1 Introduction a word (also called anitem) was allotted a predeter-v mined number of character positions,each unused position being iilled with a space symbol.y The use `of suchstandard word lengths, however, usually meant that the standard lengthadopted had to be the length of the maximum anticipated item ofinformation. The use of ice standardkword lengths thus resulted in agreat deal of waste storage space. Therefore, computing systems andcoding techniques have had to be devised which allow the use of variablenon-standard maximum length items. .The items are-called non-standardbecause item lengths may be different for the different items. The itemsare termed variable because each item may assume vany number of places,not exceeding the maximum allotted to it.

A multiplication system operating on such items of variable non-standardmaximum length creates additional problems. In order that operations maybe performed thereon in an etcient way, once the effective beginning ofeach item of information is detected, knowledge relative to thisbeginning point which may be changed during the operation should beretained While the operation with these items is being performed.Further itis desirable to reduce manipulation of the partial productsobtained. One such manipulation which it is particularly desirable toreduce is that of shifting the partial product.

1.0 Introduction Cdl/Wm 2.0 Detailed description 2.1 Description ofcircuits-Preliminary--- 3 2.2 Description of circuits of Figure l 3 2.3Description of circuits of Figure 2 6 2.4 Description of circuits ofFigure 3 9 2.5 Description of circuits of Figure 4 ll 2.6 Description ofcircuits of Figure 5- 14 2.7 Description of circuits of Figure 6--- 173.0 Operation 3.1 Staticizing instruction 19 3.1.1 Status level R001high 19 3.1.2 Status level R002 high 20 3.1.3 Status level R003 high 2l3.1.4 Summary of status levels 22 3.2 Performing operation M(Multiplication 22 3.2.1 Status level RS high 23 3.2.2 Three possibleconditions under RS high 3.2.2.1 One or both characters space 25 3.2.2.2ISS before other charaeters 26 Y 3.2.2.3 Non-space characters 27 3.2.3Status level RI high 27 3.2.3.1 First multiplier digit zero- Rl-ROMsequence L 27 3.2.3.2 First multipliery digitnot-zero-RI-RO sequence 283.2.3.3 Conclusion of RI status level 30 3.2.4 Status level RO high 3l3.2.5 RI-RO-RI sequence 32 3.2.6 Status level RN high (renewmultiplicand and partial produci; address) 32 3.2.7 Status level ROMhigh 33 3.2.8 Status level RD high 36 3.2.9 Status level ROM high again36 3.2.10 Status level RI high with a zero multiplier digit after anon-zero multiplier digit 37 3.2.11 Completion 38 3.3 Flow of statuslevels and summary of operation f '38 3.4 Zei-os in the multiplier 414.0 Conclusion 42 It is, therefore, an object of this inventionto'provide an improved multiplication system for quantities representedby electrical signals in a binary typel code.

Another object of this invention is to provide an improvedmultiplication system, which system operates automatically withoutspecial programming.

Still another object of this invention is to automatically multiplyquantities coded as variable non-standard maximum length items.

An additional object is to provide an improved system for multiplyingelectrically represented quanties at a high rate of speed wherein thestorage locations of the least significant characters of each of thequantities need be ascertained only once.

Yetl another object to this invention is to automatically multiplyquantitiessimply and efficiently at a high rate of speed by the use ofan improved process, which provides,V in effect, a shift.

in accordance with the invention, an arrangement'is provided whichoperates on electrical signals representing binary coded decimalinformation, The storage locations of the least signicant digits of themutiplier and the multiplicand are ascertained after search and enteredin storage at the beginning of the multiplication operation.Multiplication is then performed by repeated additions and apparent4shifts. The multiplicand is first added sequentially digit by digit toitself a number of times corresponding to the first decimal digit of themultiplier. At each addition, the successive decimal digits of thevmultiplicand are sequentially added to the corresponding decimal digitsof the resultant partial product.

When the succession of serial additions for a particular multiplierdigit is completed, the address, that is, the storage location, of themultiplier in the multiplier storage, lis advanced by one. Also, thepartial product address is advanced by one. The address of the leastsignificant digit of the multiplicand is retained in storage withoutchange. Thus, when each more significant multiplier digit is broughtout, the multiplicand is added to successive more signiiicant digits ofthe prior partial product. The effect is equivalent to shifting thepartial product to the right. However, unnecessary manipulation of thedigits of the partial product is avoided.

The novel features of this invention as Wellas the inventionitself,'both as to its organizationy and method of operation, will bestbe understood from the following description, .when readvin connectionwith the accompanying drawings, in which like reference lnumerals referto like parts, in which: v

FIGURES v1 to 6, inclusive, constitute a schematic diagram of thecomponents in block form of so much of a computer embodyingthejinvention as provides .a clear understanding oflthe inventionitself;

FIGURE 7 is a ilow diagram of certain high status levels (a level beingone of two bi-valued voltages as a particular output);

FIGURE 8 is a drawing showing the manner in which the FIGURES 1 to 5 areto be placed to form a complete drawing of this invention. When placedin the proper order FIGURE 1 is at the top with FIGURE 2 immediatelybelow, FIGURE 3 below FIGURE 2, FIGURE 4 below FIGURE 3, and FIGURE 5 isat the bottom below FIGURE 4 and;

FIGURE v9 is a block diagram illustrating the maior components ofFIGURES 1 to 5 inclusive.

2.0 Detailed description 2.1 Description of circuits-Preliminary Thepresent invention is embodied in a computer which is more fullydescribed in a copending application entitled Information HandlingSystem by one of the present applicants, Lowell S. Bensky, Serial No.478,021, tiled December 28, 1954. It may be noted that the variouscomponents bear similar designations and the same reference numerals asthe similar components in the drawings inthe said Bensky application.The said Benskyv application describes a computer in detail includingvarious operations amongwhich is an operation for multiplying numbersstored in the memory of the computer. This multiplication operation isthe one involved here. Thus, the computer is shown herein in abbreviatedform, including only so much of the detailed elements as provide a clearand ready understanding of this invention.

In this computer, the data upon which the computer acts may be stored ina static memory which, by way of example, may comprise two memory banksdesignated respectively, the left high speed memory and the right highspeed memory 16 (FIG. 3). Hereafter the abbreviation HSM is employed forthe high speed memory. Each memorybank maybe of the type employingmagnetic cores and may be assumed to include address circuits. Eachmemory bank also includes read-out and write-in circuits which may berespectively actuated by pulses or high levels. y

Upon the occurrence of a pulse at the appropriate circuit, the memory isplaced in condition to read-in information applied to its information incircuits or the memory is placed in condition to supply information atits information out Acircuits (read-out). The information in or out isin the form of binary digits of information or bits as represented by anelectrical signal (a voltage level) on one of several leads. Seven bitsin this instance may be stored at each address and written in orread-out in parallel. However, one of these seven bits is a parity bitand is ignored in describing the present invention. As will appear morefully hereinafter a series of timing (that is, clock) pulses areprovided in cycles of approximately 20 microseconds. It is assumed thatthe read-in and read-out circuits, although primed for addressing thelocation of the information, are further actuated internally only uponthe occurrence of the timing pulse designated T5. In formation may bereceived from or fed out lof the memory throughout the period from thefifth to the sixth timing pulses T5 to T6. In the alternative a vacuumtube type memory such as a selectron or any other type of random accessmemory may be employed.

It may be noted that the employment of two banks 0f the memory and theuse of other certain details involved are not essential to the inventiondescribed and claimed herein. But these details are shown and describedby way of clear, explicit and full example.

2.2 Description of the circuitsk of FIGURE I In a known manner, aprogram drum PD (FIG. l) is supplied with a timing track and a resettrack. The program drum LPD is preferably a magnetic coated drumcontinuously rotated. As the drum rotates, pulses from the timing trackare generated in reading heads positioned adjacent to the timing track.The pulses are in synchronism with lines of information written on thedrum in the form of binary numbers magnetically stored in twelve datachannels. With the occurrence of every other pulse from the timingtrack, a timing pulse generator TPG generates a series of nine timingpulses designated at T1 to TS and TSa, respectively. The particularmanner of generation of timing pulses is shown more fully in the saidcopending Bensky application and especially the manner whereby everyalternate pulse from the timing track is suppressed. This latterfeature, although highly useful in providing greater compression ofinformation on the drum, requires no further description for thepurposes of describing the present invention. The reset track on theprogram drum PD provides a fiducial pulse from which the lines on thedrum are counted.

Six of the data channels on the program drum PD are read by six leftreading heads and amplifiers 51 and the other six data channels are readby six right reading heads and amplifiers 52. A gate receives the pulsesfrom the reset track of the program drum PD and applies it to the resetterminal R of a drum counter DC.

The gates herein areall logical and gates, and are indicated byrectangles with the priming leads indicated by arrows directed towardthe rectangle and the output by an arrow leaving the rectangle. The gate150 is a two input and gate. In addition to the input from the resettrack another input to the gate 150 is indicated which, for the purposesof the present application, may be considered always high (having a highvoltage level), and the gate therefore always open. The drum counter maybe a counter of twelve stages.

Each of the counters and registers herein may be flipflop counters orregisters. The trigger terminal T of the drum counter DC receives theoutput of an or circuit. This or circuit receives two inputs. One, thefirst timing pulse T1 and the other, the fifth timing pulse TS. In thedrawing of this application as in the Bensky application, a specialconvention is adopted for the showing of an or circuit. According tothis convention the inputs to the or circuit are indicated by arrowheadsconverging to a point which is the center of a small circle.

A drum address is provided containing twelve (l2) bits of addressinformation. This input is merely indicated by the letters Drum AddressSince this particular function is not deemed essential for the purposesof describing the present invention. This drum address may, for example,be provided by a counter or a register having l2 Hip-flop stages such asis described in the abovementioned Bensky application. The 12 bits ofaddress information from the drum address are applied to 12 inputs of anequal circuit 50. Another 12 inputs to the equal circuit 50 are from the12 iiip-op stages of the drum counter DC.

kA Hip-flop is a circuit having two stable states, that is conditions,and two input terminals, one of which may `be designated as a reset, theother set. The flip-flop may assume the set condition'by application ofa high level (or pulse) on the set input terminal S or the resetcondition by the application of a high level (or pulse) on a resetterminal R. Two outputs are associated with the flip-flop circuit whichare given the Boolean tags of one and zero. If the Hip-flop is in itsset condition (that is, set) the one output voltage is high and the zerooutput voltage is low. Unless otherwise indicated, the outputs from theflip-flop are taken from the one terminal. yIf the flip-flop is reset(that is in its reset condition) the one terminal is low and the zeroterminal isehigh. A flip-flop may also be provided with a triggerterminal T. Application of pulses to the trigger terminal T causes theiiip-op to assume the other condition from 'the lone it was in when thepulse was applied. Counters are formed from Hip-Hops ina known manner.

In the drawing of this application, multiple leads are indicated bydotted lines. Each of these multiple leads carries, as the'machiueoperates, a binary digit of informa-I gates tion having only twopossible voltage levels, one high, and one low. Therefore the linesthemselves are sometimes designated as bits (binary digits ofinformation).

The equal circuit 50 may comprise a group of and gates, one for eachpair of output leads from the corresponding bits of input informationfrom the drumaddress and the drum counter DC, respectively. The outputsof each of the 12 and gates are then applied to a single and gate.Accordingly, the equal circuit 50 has a pulse output, if and only if,the binary number of the address is the same as the binary number of thedrum counter DC.

A drum line match ip-op F125 receives at its set terminal S the outputof the equal circuit 50. Note that the stylized double F is employed inthe drawing to indicate a ilip-tlop. The output of a three input gate243 is coupled to the reset input of the drum line match flipiiop F125.Inputs to the three inputfand gate 243 are received from the eighthldelayed timing pulse T8Q, from the status level IC (FIG. and from athird input lead, herein designated by the symbol high The highdesignation is given sincethroughout the multiply operation, which isthe subjectof this invention, a high input voltage level is maintainedat that particular input.

Several status levels, such as IC, are provided, oniy one of which ishigh at any given time. The selection and provision of the variousstatus levels will be described in greater detail hereinafter inconnection with FIG. 5. For the present,- it is suflicient'to note thatamong thestatus levels provided in the interest of the presentapplication are those designated as follows:

Rein, Renz., Roos, Rs, at, ROM, no, RN, RD, and 1C The one output fromthe drum line match flip-flop F125 is applied to a gate 142, to a gate242, and to one of the inputs to the timing pulse generator TPG. In thisapplication, junctions between leads are indicated by an arrowhead atthe junction, which indicates the direction of electrical signal orinformation ilow. Each ofthe 141 and 242 is a two input gate andreceives as the second input the second timing pulse T2. It may be notedthat the gates 142 and 242 provide the same output and theirfunctioncould be combined to one gate. Such a combination could also be made inother instances contained herein. The output of gate 142 is applied toboth the left and right reading heads and ampliers 51 and 52 and may beconsidered to control, or gate, the outputs of the reading heads andamplifiers.

The output of the gate 242 is coupled through an or circuit to thetrigger input terminal T of a six stage counter designated as a programsub-counter PSC. A two input and gate 244 also has its output coupled tothe last mentioned or gate tothe trigger input terminal T of the programsubcounter PSC. This latter gate 244 receives as one input the 'secondtiming pulse T2. The second input is provided by the output of a y'threeinput or gate, the three inputs of which are R001,

R002, and R003. The reset input to the program subcounter PSC isprovided by the output of a two-,inputy orV circuit. One input to thisorf circuit is provided by the output of the three-input and gate 243.Thus the program subcounter PSC reset simultaneously with the drum linematch ip-op F125. The other input to the or circuit is provided by theoutput of a twoinput gate G2239. The two inputs to the gate G239.'aresupplied by the status level R003 and the timing signal T7,respectively. n A first set of six two input and gates 630 are providedand a second set of six two input and gates 630e are provided.` Eachgate of the set of `gates 630 and 630e, respectively,` receives oneinput from the output of a two input and gate 62.9.l Each of'the gates630 also receives a second input from respective one of six of the sevenoutputs of the program subcounterpPSC (the seventh output, the paritybit, is ignored for purposes of this application as mentioned above).Also 'each of the six gates 63011 receives one input from a differentoutput of the seven stages of the program subcounter PSC. Note thatbetween the gates 630 and 63041 the output leads from the programsubcounter are indicated as branched, a similar convention beingemployed for multiple leads as shown here. One input to the'gate 629'isprovided by the rst timing pulse T1. The remaining input to the gate 629is received from the output of an lor circuit, the inputs to which arethe status leveis R00l, R002, and R003 (FIG. 5). The outputs of each ofthe six gates 630 are coupled to the address circuits of the left HSM(FIG. 3) which will be deserbed in conjunction with FIGURE 3. Similarly,each of the six leads from the output of the gate 63051 are coupled tothe address circuits of the right HSM 16 (FIG. 3). his also will bedescribed in conjunction with FIG- RE 3. f

An .operations 0 register 30 of six stages is utilized. The dii'erentoutputs of the 0 register are connected to control an operation matrixOM. The reset terminals R of the 0 register 30 receive the output of atwo input and gate 1401. One input to the gate 1401 is from the statuslevel R001, and the other input is from the rst timing pulse T1. The setterminals S of the 0 register 30 receives the various outputs of a setof six gates 1402, each of which is a three input and, gate. One inputto each of the gates 1402 is provided by the status level R001 and asecond input to each of the gates 1402 is provided by the sixth timingpulse T6. The third input to each of the gates 1402 is received from oneof the six output leads of the left HSM 15. The operation matrix OM isva matrix which selects a diiterent output lead depending on the sixbits entered into the "0 register 30. The particular output of theoperation matrix of interest in this application, namely, multiply, isindicated as an operation .level M. The other outputs of the operationmatrix are of interest with respect to other operations which the entiresysternmay perform. The operation matrix therefore selects the operationto be performed by the computer in response to a coded input from the "0register 30 which input may be withdrawn from either the lett or rightHSM 15 or 16 (FIG. 3) as described. hereinafter.

2.3 Description of circuits of FIGURE 2 Reference is made to FGURE 2which is to be placed immediately below and adjacent to FIGURE l as isindicated by the block diagram of FiGURE 8. With this particular layout,the lines from FIGURE l to FIGURE 2 are continuous.

The reset terminals R of an A register 26 receive the output of a twoinput and gate 481 through an or circuit arrangement. One input to thetwo input and gate 481 is the status the two input and gate 481 is thesecond timing pulse T2. Also connected into the reset input of the Aregister through the or circuit arrangement is a three input and gate404. The rst input to the and gate 404 is provided by the rst timingpulse T1. The second input to this gate is provided by the status levelRS. Third 404 is received from a space left flip-flop F911 (FIG. 4).

The six low order stages of the set :terminals of the A register 26receive the outputs of a set of six three input gates 402. One input ofeach of the gates 402 is from the status level Ki and the second inputof each gatel is from the sixth timing pulse T6. The third input to eachof the six gates '402 is from the six respective outputs from the rightHSM 16 (FIG. 3). The remaining three terminals S of the A register 26receive, respectively, the outputs of' a set of three input and gates405. One of the inputs to the gates 405 isl a status level R002 and asecond input to each of the vgates 405 is a sixth timing pulse T6. T heremaining (third) input to the gates 405 is respectively from three ofthe six bits of the output from level R001, and the other input to theleft HSM (FIG. 3). A set orr nine five input and gates 414 have theiroutput connected through the or circuit to the set input through an orcircuit along with the Outputs from the gates 402 and 465, respectively,to the set input of the A register 26. One input to each of therespective gates 414 is provided by the respective outputs of the Acounter 1t?. Pruning inputs to each or the gates 414 are supplied by theoperation level M, the status level RS, the second timing pulse T 2, andthe one output of 'the space ieft flip-flop F311 (FTG. 4). Thus tosummarize, the A register may receive nine bit inputs from either theset of gates 414 or the sets of gates 461 and 49S, in combination.

The remaining three bits of the output from the left HSM 15 (Fi-G. 3),respectively, are applied to the three gates of a set of three, twoinput gates 544. Three of the higher order set terminals S,respectively, of a i3 counter 11 receive the three respective outputs ofthe gates 544. The set terminals S of the other six lowest order stagesof the B counter 11 receive, respectively, the six outputs of a set ofsix two input gates 547. Each of the gates 547 receive one input fromeach of the six outputs of the right HSM 16 (PIG. 3). Second inputs toeach of the gates 544 and to the each of the gates 547 are from theoutput of the two input and gate 512. One input to the gate 512 is fromthe status level R962 and the other input to the two input and gate 512is from the sixth timing pulse T6.

A twelve stage C register 2S and a nine stage C counter 12 are provided.The six lowest order stages of the C counter 12 have their respectiveset terminals S connected to receive the outputs of a set of six twoinput and gates 318. Similarly, the set terminalsS of the six lowestorder stages of the C register 28 are connected to receive the outputsof a set of six three input and gates 439. Each gate of a set of gates31S and 430 receives as one input the status level R033, and at thesecond input the sixth timing pulse T6. Further, each of the sets of sixgates 31S and 43?, respectively, receive as their third inputs the sixoutputs of the right HSM 16, respectively.

The remaining three high order set terminals S of the C counter i2 areconnected, respectively, to receive the outputs of a set of three, threeinput and gates 324. The gates 324 have as one input the status levelRMS, and as the second input the sixth timing pulse T6. In thisinstance, the third input to each of the gates 324 is from therespective three lowest order outputs of the left HSM 15. These threeoutputs of the left HSM 15 are also supplied to three lower order gatesof a set of six three input and gates 436. The remaining three outputsfrom the left HSM 15 are applied to the other three gates of the set ofsix gates 436 which have their output terminals connected, respectively,to thev set terminals S of the three highest order stages (29, 210, 211)of the C register 2S. The other three outputs of the set of six gates436 are connected to the remaining set terminals S, respectively, of theremaining three stages of the C register 23, namely, 26, 27, and 2abits, respectively. The remaining two inputs to each of the gates 436are from the status level 126% and the sixth timing pulse T6.

Although the outputs from the memory banks are apparently read into manyplaces at once, the fact is these outputs are distributed during thedifferent status levels. Note, for example, that the entry to the ninelowest order stages of the C register 28 is the same and is made at thesame time as that to the nine stages of the C counter 12 and from thesame memory outputs.

The reset terminals R of hte C register 28 receive the output of the twoinput and gate 442. Two inputs to inputs trom the iirst timing pulse T1and from the status l levelRtiiBl. The output of and gate 502, inaddition to being coupled to the reset input of the B counter 11, is asoconnected to the reset terminal R of the A counter 1i).

The reset terminals R of the C counter 12 are connected to receive theoutput of a two input and and gate 223 having as one of its inputs thestatus level Rtlilt and the and the second of its inputs the firsttiming pulse T1. As is described more fully in the said copending Benslyapplication, the C Vcounter 12 is a true counter made up of iiip-ops andis rev-ersible. However, for the purposes ot the present application, itmay be assumed that the C counter 12 is always in its additive state andcounts up. Thus the input to the add portion of the C counter is merelyindicated by a high level input. In this manner, as will be laterdescribed more fully, the C counter will count upward from the leastsigniiicant digit address of the partial product during the multiplyoperation. The trigger input to the C counter 12 is supplied by artourinput an gate 361. The fourvinputs to the gate 3591 are received,respectively, from the operation level M, from the status level RI, thesecond timing pulse T2, and finally from the nines counter notnineoutput (FG. 5), respectively. Also providing an input through an orcircuit along with the output from gate 391 to the trigger terminals Tof the C counters 12 is a two input and gate 3% receiving its priminginputs from the second timing pulse T2 and from the status level ROM.

rThe nine bit outputs from the A register 26 are each connected to oneof the inputs of a set of two input and gates 514. Remaining inputs toeach of the two input and7 gates 514 are provided by the output ofanother two input and gate 510. YTwo inputs to the and gate 510 are,respectively, the status level R603, and the fourth timing pulse T4. Thenine low order bits from the C register 28 are applied to eachrespective gate of a set ot nine two input and gates 3GB. And gates 308are primed by an additional gate 395 receiving priming inputs in turnfrom the status'level RN and the fourth timing pulse T4. The output ofthe Vgate 303 is connected through an or circuit along with the outputsof gates 31@ and 324-, respectively, to the respective set terminals ofthe C counter 12.

The output of the C counter is connected to the respective inputs ofeach of two sets of gates 660 and 418 respectively. Gates 660 are eachprimed by the output of a gate 696 (FIG. 3). The gate 696 (FIG. 3)receives priming inputs from the operation level M, the first timingpulse T1, and from the one side of the 29 bit stage of the C register28. The final priming input to the gate 696 is provided bythe output ofan or circuit receiving inputs from any one of the status levels RI, RO,or RD, respectively. Each of the gates 418 along with the gates 490 areprimed by the status level ROM and the eighth timing pulse T8. Gate 413provides an output from the output of the C counter through an orcircuit to the set inputs of the C register 28. Similarly, the output ofgate 490 is connected to the 29 bit stage of the C `register 28.

The trigger terminals of the A counter 10 receive inputs from theoutputs oan or circuit receiving inputs from the Igates 504 and 5%5. Thegate 504 receives priming inputs from the operation level M, thestatus'level RO, and the second timing pulse T2. On the other'hand, thegate 505 is primed by the operation level M, the

status level RS, and the third timing pulse T3 to provide 9 actuated bythe output of a two input gate 511 receiving inpu-ts from the statuslevel RN and the first timing pulse T1. The outputs from the A counter10. provide the inputs, respectively, to each of the nine sets of twoinput gates 64I?, as well as to one of theinputs of each of the set ofnine gates 414 as mentioned above. The remaining input to the set ofterminals of the two input gates 640 is received from the three inputgate 6&9. One of the inputs to the gate 599 is received from the outputof an or circuit having inputs from the operation level M, the firsttiming pulse T1 and from the output of an or circuit receiving inputsfrom either of the status levels RO or RS.

In a similar manner the nine bit outputs from the B counter 11 areconnected to the inputs of nine sets of two input and gates 670.Remaining inputs to each of these and gates 670 is received from theoutput of a three input gate 5213 (FIG. 3). Referring to FIG. 3,

these three inputs to gates 693 are seen to be from the operation levelM, the iirst timingk pulse T1, and from the output of an or circuitreceiving inputs from either the status levels ROM or RS.

Also seen in FIGURE 2, are a pair of gatesl 841 and S72. Each of thesegates receives the output of an or circuit which in turn receives inputsfrom either the been-in RN flip-hop F1111 (FIG. or from the ninescounter not-nine logical output from the nines counter (FIG. 5).Similarly, each of the gates 841 and S72 rcceive priming inputs from theoperation level M. Each of the five gates comprising the set receivethese latter two priming inputs. Each of the set of five gates 841 alsoreceives an input from the second binary coded decimal converter 17B(FIG. 5). The gate 872 receives additional priming inputs from the RIstatus level, and the second timing pulse T2. The output of the gate 872is connected through an or circuit to the set input of the 24 bit of theR register 19 (FIG. 3). Similarly, each of the gates 341 is connected totheir respective set inputs of the R register 19 (FIG. 3).

The gates 660 and 670 (FIG. 2) respectively, connect outputs ofthe Ccounter 12 and the B counter 11 through an or circuit along with aninput from the gates 630e (FIG. l) to the address input of the right HSM16. In a similar manner gates 640 connect the output of the A counter tothe address input of the left HSM (FIG. 3).

2.4 Lescriptioiz of Zhe circuits of FIGURE 3 perform similar functions.Therefore, only the left hand portion of the figure is described indetail and fthe corresponding parts, together with the differences andcon# ncctions will be pointed out as the'description progresses. Theleft HSM 1S receives as inputs to its address circuits, as describedabove, the nine outputs from either of stage of the C register 2S (FIG.2). The third input to the left read-in gate 721 is from the Zero outputof the 29 bit stage of the C register 28 (FIG. 2). The fourth and -nalinput to the left read-in gate 721 is from the RI status level.

Each of the gates 722 receive their second inputs respectively, from thesix outputs of a left register v13, termed the L register. Six outputsof the six left reading heads 51 (FIG. 1) are applied throughorfcircuits to the six set terminals S respectively, of the L register18 (FIG. 3). Additional inputs `to the set terminals S of the R register1S are received from' the output of a set of six gates 717 (FIG. 5)which couple the output of the lirst binary coded decimal converter 1711(FIG. 5) to the L register 13 set input. The iinal input for the Lregister 18 is from the `output of `a gate 749 (FIG. 3) to the fifthstage (24 bit) of the L register 1S. The gate 749 receivesV priminginputs from the second timing pulse T2,'the operation ievel M, and thestatus level RI. A final priming input is received from the output of anor circuit receiving inputs ltrorn either the one output of the been-inRN flip-flop F1111 (FIG.V 5) or the output of a second or circuit. Thesecond or circuit receives inputs from either the RS status level orfrom the nine's counter not-nine output from the nines counter 45 (FIG.5,).

The read out circuits of the left HSM 15.are actuated by the output of aleft read-out gate 730. `The left readout gate 730 is activated by twoinputs from the outputs of two or circuits, respectively. v The rst ofthese or circuits receives inputs from either the status levels R001, orRS. The iinal alternative input to this last mentioned ."or circuit isprovided by the output of a second or circuit receiving inputs fromeither the status levels R002,

RO', or from the output of a third or circuit. This third or circuit mayreceive the outputs of either the R003 status level, or the ROM statuslevel. The remaining input to the left read-out gate 72:0 is alsoreceived from the output of an additional plurality of or circuits. Thefirst or gate of this 4additional plurality receives inputs from theR001 status level, from the "0 output of the 2"y bitv of the C register28, or'from the output of an additional or circuit receiving inputs fromthe R002 status level, R003 status level, or the operation level M.

By way of summary, the left readaout gate has a high output whenever anyone of the status levels R001, R002 and R003 is high. The left read-outgate 730 is also actuated during the operation level M (multiply) whenany of the RS, RO, or ROM status levels are high.. Components in theright hand portion of FIGURE 3, corresponding to those in the left-handportion, are as follows: the Yright HSM 16 corresponds to the left HSM15; the right yregister 19 corresponds to the left register 18; however,

an` exception exists in that the set terminals S of the R register 19receive the output of the right reading heads 52 (FIG. l). Further,gates 851 correspond to the gates the two sets of two input gates 640(FIG. 2) or 5630 (FIG. 7

l) through or circuits.

A six bit input to the left HSM 15 information-in circuits (abbreviatedin the drawing as info-in), is received from the six outputs of a set ofgates 722.A` One input to each of the gates 722 is from the output of athree input gate 799. One input of the gate 799 is, for the purposes ofthis application, a continuous high level input; Remaining inputs to thegate 799 are provided by the fifth timing pulse T5 and the output of aleft read-in gate 721. One input to the left read-in gate 721 may betaken as always high, for purposes of the present application so thatthe left read-in gate 721 may be considered as alwa s primed thereby. Asecond input to the left readin gate 721 is taken from the Zero outputof the 211 bit 722; gate 899 corresponds to the gate 799; also the rightreadin gate-S50 corresponds to the left read-in gate 721.

vAnother exception exists here in that the right read-in gate 850receives an output from the one terminal rather than the zero terminalof the 211 and 29 bits, respectively, of the C register 28.

A three input gate 860 is provided having an output Which'is applied tothe reset terminals R of both the L register 13 and the R register 19.This last-mentioned output is designated as XX. The gate 860 has itsiirst input from the status level RI;` Second and third inputs,

respectively, are from the irst timing pulse T1 and an finput which maybe designated as continuously high, for purposes of this application.The right readfout gate $62 corresponds to' theleft vread-out gate 730to provide an output whenever any one of the status levels R001, R002 orR003 is high. In addition, high status levels ROM, RO, or RS alsoprovide an output during the high operation level M. A4 gate S63 islconnected through an S62 to the read-out circuitry of the right HSM 16.

Yconverters 17h (FTG. 5) are unequal.

amatori.

11 or" circuit along with the output of the right read-in gate The gateS63 is a two-input gate receiving these inputs from the operation levelM and the status level RD.

The outputs of the L register 1S and the R register 19, in addition tobeing connected through. the gates 722 and S51, respectively, to theleft and right HSM 15 and 16, respectively, are also connected to atirst equality circuit 20. This lirst equality circuit 26 is actuated bythe seventh timing pulse T7, to generate an error signal when theresults of the iirst and second binary coded decimal A second priminginput to the iirst equality circuit Ztl is received from the Rl statuslevel. Thus, the equality circuit 26 will compare the two results of asurn produced in each of the adders (converted by the binary codeddecimal converters 17h (FIG. 5)), the results of which are stored in theleft and right registers 13 and 19 (FlG. 3) during this Rl cycle, uponthe occurrence of the seventh timing pulse T7. In the event ofinequality, an error signal may be generated to be used `to indicateerror as desired.

2.5 Description of circuits of FIGURE 4 Reference is made to FiGURE 4which is to be placed immediately below FGURE 3 as indicated in FIGURE 8so that the lines from one figure to the other are continuous.

In the description of this figure as in the description of FIGURE 3,since the left and right halves of the figure contain a great deal ofsymmetrical components, a description will be givenlonly of the leftside. Then comments will be made as to the similarities, changes, oradditions necessary in the right side of FTGURE 4.

A Y'register 13 of six stages is provided. The set input terminals S ofthe Y register 13 receive the output from the left HSM.15 through a setof six, two input and gate 911. Remaining inputs to each of the andgates 911 is provided bythe output of an or circuit having inputs fromthe outputs of two gates 913 and 919, respectively. Gate 91S receives aninput from the sixth timing pulse T6, from the status level RS, and fromthe one output ofV a space lett ip-op F911 (FTG. 4). The gate 919receives inputs during the RO status level and from the sixth timingpulse T6. Arthird input to the gate 919, for the purposes of thisinvention, may be considered as always havin@ a high level or condition.

The -outputs olf three gates 9111, 992, and 963, respectively, are eachcoupled through an or circuit to the reset input of the Y register 13.Each of the gates 901, 962, 993, respectively, receive a priming inputfrom the fourth timing pulse T4. The irst of these gates 9111 receivesadditional priming inputs from the status level Rtlt'and from the outputof an or circuit receiving inputs from the status levels R001 or Rl. Thesecond of these gates 9132 receives additional priming inputs from theRS status level and from the one output of the space left tiip-op F911.vThe third of these gates 963, receives additional priming inputs fromthe RO status level and from an additional input which may be consideredhigh for the purposes of this invention.

The output of these three gates 961, 992, and 983, as mentioned above,is coupled through an or circuit to the reset input of the Y reigster13. Also coupled t the reset input of the Y register 13 along with theoutput Vof the above mentioned or circuit is the output of a gate 1130(FlG.

The gate 113%1 receives priming inputs from the eighth timing pulse T8,the operation level M, and from the one output of the EOBO flip-liepF1116 (FIG. 5 The output `of the gate 113% is also contrectedl Crt Theoutputs of eachof the six stages of the Y register 13 are connected tothe respective inputs of each of a set of six gates G27 (FIG. 5), thenceto be coupled to one of the inputs `of the duplicated adder and binarycoded decimal converter circuits 17 (FiG. 5). Each of the six bits ofthe Y 'register is also connected to a group left symbol recognitioncircuits 22. rThese symbol recognition circuits 2?. comprise two orocircuits R922 and R923. Each of the or circuits P322 and 11%?, receivesa different one of the six inputs from each o the six stages of the Yregister 13. The first of the or circuits R922 recognizes the absence ofan item separation symbol in the Y register. Thus the output of the gateR922 is termed NOT ISSL. This NOT ISSL output is connected to the inputof an inverted 111. Due to the functioning of the inverter 111, itsoutput indicates the presence of an item separator symbol in the Yregister. Thus the output of the inverter 111 is termed ESSL andprovides a high level signal when an item separator symbol is receivedin the Y register from the lett HSM 15 (FIG. 3'). Accordingly, this iSSLoutput lead is high, it' and only if, the inputs to the recognizedNOT'ISSL gate, R922 receives a coded item separation symbol.

Continuing, the ISSL output is applied to a two input gate 37. A secondinput to the gate 937 is provided by the output of a gate 941. One inputto the gate 941 is in turn provided by the eighth timing pulse TS. Forthe purposes ot this application, the remaining input to the gate 941may be considered to have a continuous high level input. The output ofgate 93/ is connected to the set input of the ISSL Hiphop F916'.` Thesymbol recognition circuit contained in the symbol recognition circuitsR923 `are termed space recognition circuits. The logic herein utilizedis again an inverted type logic. These logical or circuits are arrangedso that an output is provided, if and only if, their inputs from the Yregister is not a coded space symbol. This NOT SP1. lead is applied t0an inverter i9 and the output of the inverter is designated SPL.Accordingly, the SPL output lead is high, if and only if, the input tothe recognizedNOT SPL circuit (that is, the output of the Y register 13)is a coded space symbol. The SPL output of the inverter` I9 is suppliedto one input of a three input gate 93S. The second input to the gate 938is provided by the eighth timing pulse T3. Third input to the gate 938may, for the purpose of this application, be considered as always high.The output of the gate 938 is connected through an or" circuit to theset input of the space left iiip-op F911.

The components from the right-hand portion of FIG- URE 4 correspondingto those of the left hand portion are as follows: Z register 14corresponds to the Y register 13; gate 1032 corresponds to the gate 911;gates 163i) and N31 correspond, respectively to gates 919 and 91S,

vwith the exception that certain of the logical inputs for two gates193@ and 1631, respectively, are diierent. Thus, both gates 11139 and11131 receive priming inputs from the sixth timing pulse T5.. Also gate1031 receives a priming input from the status level RS, but in thiscase, the` gate 1031 receives additional priming inputs from the oneoutput of a space right tlipdiop F1o-@3, and from another .input whichmay be consideredas always high. Similarly, the gate 10341 receives apriming input from the zero output of the end of operand right `flip-hopF1010, from another priming input which may 4be considered always high,and from a inal priming input which receives the` output of an or"circuit. This or circuit may receive inputs from the ROM, RO, or RDstatus levels. Additional similarity between the right-hand portion andleft-hand portions of FIGURE. 4 are that the right symbol recognitioncircuits 23 correspond to the left symbol recognition circuits 22.,recognition gate RMS@ correspond to the recognition circuits R922, andrecognition gates R1052 correspond to the recognition gates R923.Simiiarly, the inverters 112 and 14, respectively, correspond to theinverters 111 and I3, respectively, the space corresponding inputs of aset of four gates G17.

cuit D56 to the reset terminals R of kthe Z register 14 through aplurality of or circuits are the gates 11141, 11142, 19433, 1055, 1968,and 11169. Gate 1(311 is a twoinput gate connected to receive thepriming inputs from both of the outputs of two or circuits. The first ofthese or circuits receives inputs from the R001 status level, or fromthe ROM status level. The second of these or circuits receives inputsfrom either the yfourth timing pulse T4 or the eighth timing puise T8.The gate 1G42 is also connected to receive inputs from the status levelRS, fromthe one output of the space right iiip-op F1655, and from thefourth timing pulse T4.

Gate 1h43 is a three-input gate receiving the first of the three inputsfrom the fourth timing pulse T4. The second of the inputs is derivedfrom the status level RO, whereas the third and nal input is derivedfrom the zero output of the end of operand right flip-hop F1016.

yThe gate 1069 is a four input gate receiving inputs from the operationlevel M, the status level RD, and the eighth timing pulse T8. The fourthand final input to the gate 1669 is received from the SPR output of theinverter I4.

The outputs of the gates 11155 and 1065, respectively, are connectedthrough an or circuit, not only to the Z register 14, but also to theset input of the end of operand right dip-flop F1010. These gates 11365and 1068, respectively, receive a common input from the eighth timingpulse T8, and from the operation level M. In addition, the gate 11155receives priming inputs from the RO status level and from the SPR outputof the inverter ld. Similarly, the gate 11155 receives additionalpriming. inputs from the ISSR output of the inverter 112, and from theoutput of an or circuit receiving inputs from either the status levelsRO or RS. The output of the Z register is connected through a set oftwo-input gates 1048 to the input of a set of six gates G21. Theadditional input to each of the gates 1048 is provided by the operationlevel M.

` The SPR output from the inverter I4 is also coupled to prime the gate11157. Gate 1057 receives additional inputs from the RS status level andthe eighth timing pulse T3. ln turn, the output of gate 1057 is coupledthrough an or circuit to the set input of the space right tiIp-iiopF1008. Also coupled through this or circuit to the set input of thespace right flip-flop F1008 is the output of a gate 945. The output ofgate 945 is also coupled through another or circuit along with theoutput of gate 938 to the set input of the space left flip-flop F911.The gate 945 is a three input gate receiving these three inputs from theoperation level M, the first timing pulse T1, and the status level121.1123.

The output of the right HSM 16V (FIG. 3) is also coupled to the input ofa nines complementer 21. The nines complementer 21 receives a priminginput from the output of a two input gate G13. The two input gate G13receives inputs from the sixth and seventh timing pulses 'T5-T7, andfrom the operation level M. The respective outputs of the ninescomplementer 21 are coupled to the rThe nines complementer 21 accepts abinary coded decimal digit and produces the nines complement of thedigit.

example, in the application of Spielberg and Sublette, Serial No.337,572, filed February 18, 1953, entitled Code Converter System, andissued July'9, 1957 as Patent No. 2,798,667 and which is assigned to theassignee 14 I of this invention. The priming inputs to each of the gateG17 is received from the output Vor anfor circuit. This or circuitreceives inputs from either the ROM status level or from the output ofthe space right Hip-flop F 10113. In turn, the output of each of thegates G17 is connected to the set inputs of a nines counter 45 (FIG. 5).

`A gate 944 receives inputs from the seventh timing pulse T7 andfrornthe' output of an or circuit receiving inputs from the ROM statuslevel or the RS status level.

In turn, the output of gate 944 is coupled through a plurality of orcircuits to the reset inputs of'each ofthe end of operand iiip-iiopF1ti1tl,rspace right liip-op F1068, and the space left hip-iop F911.Another gate 943 receives priming inputs from the first timing pulse T1,andl from the status level RM1. The output of the ygate 945 vissimilarly connected through a plurality of or circuits to the resetinputs of the end of operand right tiip-flop F1011), to the space rightflip-flop F1953, and to the space left flip-flop F911.

The one output of both the ISSL iiip-op F910 and the space left iip-flopF911 are connected through an or circuit to an inverter I7. The outputof the inverter I7 is connected to each of the set of six gates G27(FIG. 5). The particular connection herein will be described in moredetail with reference to FIGURE 5. In addition each of the one outputsfrom the ISSL flip-liep F9111 and the space left Hip-iop F911 areconnected through an or circuit 67 to provide a priming input to afour-input gate 948 (FIG. 5). Here again, these connections will bedescribed in more detail in the discussion with respect to FIGURE 5. Ina similar manner, the one output of the end of operand right ip-iiopF1111@ (FIG. 4) provides a second priming input to this same gate 948(FIG. 5) The remaining two inputs to the four input gate 94.18 (FIG. 5)are provided by the iirst timing pulse T1 and the status level RI. Theoutput of gate 945, in turn, is connected to the set input of a EGBOflip-flop F1110 (FIG. 5).

Note that there is no ISSR flip-flop corresponding to the ISSL flip-flopF911?.

2.6 Description of circuits U19-FIGURES is connected to a set of sixgates G21. Each of the gates 70 This complementer 21 may be of the kinddescribed, for` F3. Each of the gates G4 and G3 receives a priming inputfrom the status level RI. The first gate G4 receives its second priminginput from the first timing pulse T1 whereas the second gate G3 receivesits second priming input from a delayed third timing pulse designatedTS1/2. The output of each of the two sets ofsiX gates G27 and G21,respectively, are coupled to the inputs of an arithmetic unit 17.

The arithmetic unit comprises iirst a duplicated binary adder 17a and aduplicated binary coded decimal converter 17h. These units receive asinputs the two characters to be added during the sub-sequences ofmultiplication in binary coded decimal form along with the previouscarry, and provide, as an output, a sum in the form of a Vbinary codeddecimal vdigit and a carry (if any).

Whereas a single adder and a single binary coded decimal converter maybe utilized, duplicates are herein illustrated an adder output tlip-tlopFel.

in order to provide for checking of the results by duplicate additionand conversion. i

The adders lin may be any of the well known three Vinput type binaryadders. Similarly, r-the binary `decimal converter, may for example, beof the type as disclosed in an application entitled A Code Converter byIvan H. Sublet-te', Serial No. 307,253, filed August 30, 1952, nowabandoned. The adders Ei'7a are gated by the output of Two two-inputgates Gi@` and G11, respectively, have their output connected to the setand reset input terminals, respectively', of the adder input flip-flopF45.. Each of the gates Gld and Gill receives an input from the statuslevel Rl. Gate Gi@ receives a second input from a delayed iirst timingpulse designated Til/2 and the gate G11 receives its second input fromthe third timing pulse T3. A gating pulse to the binary coded decimalconverter is provided by the output of a gate G?. This gate receivesthree inputs, one from the operation level M, another from the statuslevel Rl, and another during the range ot timing pulses TPA to T23i. Theparticular function of these gating circuits for the arithmetic unit 17,as well as for the carry circuits about to be described below, isdescribed in some detail in conjunction with the adding of successivecharacters, in the said Bensky application.

The carry output of the binary coded decimal converter llb is connectedto the set input of a pre-carry flip-flop F1.. The reset input to thepre-carry iiip-ilop Fl is received from the output of the gate G7. GateG7 receives inputs from the seventh timing pulse T7 and from either ofthe status levels Rtli or Rl through an or circuit. The output of thepre-carry flip-flop Fl is coupled to one input of a gate G8. The gate GSreceives two additional priming inputs, one from the sixth timing pulseT6, the other from the status level RI. ln turn, the output of the gateG8 is coupled to the set input of a carry ilip-ilop F2. The resetterminal of the carry dipllop F2 receives the output of an or circuithaving alternative inputs from either of two gates GS or G6. The gate GSreceives inputs from the status level Rtldl and the seventh timing pulseT7. On the other hand, the gate IG6 receives inputs from the statuslevel Rl and the fourth timing pulse T4. The output of the carry llip-opF2 is coupled to an input of the gate G12. The output of gate Gi?, iscoupled to the carry input of the arithmetic unit i7 and receives asecond priming input from the output of the adder input flip-dop F3.

Returning back to the path of the flow of information, the sum output ofthe arithmetic unit 17 comprising the 2 to 23 bits is coupled to the setinputs of an adder output register 62 and to the input of a set of fourgates 717. A gate 11l5 provides the reset input to the adder outputregister G2. The gate Mid receives two inputs, one from the status levelRl, Yand the other from the first timing pulse T1. The output of theadder output register G2 is coupled to the input of a zero recognitioncircuit 61. The zero recognition circuit 6i, may for example, comprisean or gate receiving inputs from each of the four channels from theadder output register G2. Thus, the

zero circuit would produce an output if a high level (or one) is presenton any of the adder output register channels. vThe output of the zerocircuitd provides a priming input to a three input gate i119. Remaininginputs to the gate 1119 are provided by the status level RI and thefourth timing pulse Til. In turn, the output of the gate 1119 providesone of the priming inputs to each of a pair of gates 1131. The output ofeach of the gates 1131 is coupled to the 20 and 25 stages, respectively,of each of the L and R registers 1S and 19 (FIG. 3) The function of thisgate is if a zero is recognized, to introduce a proper alpha-numericcode representing this fact to the two L and R registers `18 and 19.This is in accordance with the operation as described in the saidBenslty application.

Two additional priming inputs the gate 1131 are provided, one being fromthe operation level M, the other being from the one output' of a EGBOilip-ilip Fill-Jil. The output of gate du, described above inconjunction with FlGURE 4, is connected to the set input of the EOBOflip-ip Flllil. The reset input of the EGB() flipfiop P111@ is receivedfrom the output of a gate M23. Gate 1123 receives two inputs, one fromthe eighth timing pulse T8, the other from the output of an or circuitreceivinginputs from any of the status levels RN, IC or Rtlh.

As mentioned above in conjunction with FZGURE 4, the output of the ninescomplementer 2l is coupled through a set of gates G17 to the set inputsof a nines counter 45. As will be described below, the ninos counter 45is used in the multiplication operation to keep track of the number oftimes the multiplicand has been added to the partial product. The resetinput to the nines counter 45 (FlG. 5) is provided by the output of atwoinput gate G1. These two inputs to the gate G1 are provided by thefourth timing pulse Td and the output of an or circuit receiving inputseither from the one output of the space right ip-iiop FlililS (FlG. 4)or from the status level ROM. Similarly, a two-input gate G2 providesthe trigger input to the nines counter d5. Gate G2 receives two priminginputs, one from the status level RN, the second from the first timingpulse T1.

Only the outputs of the 20 and 23 stages of the nines counter areutilized for reasons which will be described more fully below. Thus, thezero outputs of each of the stages 20 and 23 are coupled to .the inputsof an or circuit. The outputs of this or circuit provide an outputindicating that the nines counter is not nine, and is so labeled forsimplicity in the drawing. Similarly, the one output of each of thestages 20 and 23 (which equal nine) provide two of the priming inputs toa six-input gate S37. Three additional inputs to the gate 837 areprovided by the operation level M, the status level Rl, and the secondtiming pulse T2. The final input to the gate S37 is provided by the zerooutput of a tlip-tlop designated been-in RN flip-hop Fllill. The outputof this gate 837, which is coupled to the 24 stage of the R register 19(FIG. 3) functions, as will .become more apparent below, to enter a zerointo the R register k19 when the been-in RN flip-flop is zero and thenines counter is nine. The one output of the been-in RN dip-flip Flll ismerely indicated hy the arrow. This output provides one of the priminginputs through an or circuit to the gate '7l'7 which is connected to theoutput of the arithmetic unit i7. Also coupled to this or circuit to thegate 717 is the nines counter not-nine output. The remaining priminginputs to the gate 717 are from the operation level M and from a fourthinput which is designated as high. The set of four gates 717 is, asmentioned above, coupled to the set inputs of the L register l.

Returning `to the been-in RN hip-flop Flll, its set input is receivedfrom the output of a four-input gate 17138. The first input to the gate1138 is provided by the eighth timing pulse TS, the second input to thisgate is provided by the operation level M, and the third and fourthinputs, respectively, to the gate 1133 are provided by the status levelRI and the one output of the EOBO flip-flop Fllld. The reset input tothe been-in RN flip-op Flll is provided by the output of a two-inputgate 1139. Two inputs to the gate 1139 are provided by the third timingpulseTS and the status level Rllil.

A previous result zero flip-hop F1161 is utilized, as will be more fullydescribed below, to provide storage for a signal indicating the factthat, as the term implies, a previous result was zero. Thus the oneoutput from this ip-op is merely indicated by an outgoing arrow. Thetermination of the various connections from this one output is, ofcourse, indicated in the other portions of this circuit description,particularly with respect to FIGURE 6. The set input of the previousresult zero 17' iiip-flo-p F1101 is provided by the output of afour-input gate 1106. Three of -the inputs to the gate 1106 provided`recognition circuits. The reset input to the previous result zeroflip-flop F1101 is provided by the output of a-three-input gate 1137.One of the inputs to the gate 1137 is provided by a continuous highlevel input. The remaining two inputs to the gate 1137 are received fromfthe second timing pulse T2 and from the status level R003. It will benoted that many of the recognition circuits and storage iiip-ilops inFIGURE 5 have merely an indicated output. Certain of these outputs findtheir usage in the recognition gates for deriving the successivesequences of status levels as is shown by the circuitry of FIGURE 6.FIGURE 6 will be next considered.

2.7 Description of the ircm'fs 0f FIGURE 6 With reference to FIGURE 6the ten status levels concerned with the present operation ofmultiplication an` shown by ten leads designated as R001, R002, R003,RS, RI, ROM, RO, RN, RD, and IC. These ten leads are, respectively, theone output terminals of a set of flipflops F1293, F1292, F1291, F1280,F1289, F1287, F1290, F1286, F1284 yand F1282, inclusive, which aredesignated as the status level control lijp-flops 47. These status leveloutput leads are not carried continuously to the other figures but areindicated throughout by their appropriate reference letters.

The set terminals S of the status level control ilip-ilops 47 areconnected to receive, respectively, as itemized above, the output of thedelay circuits D1293, D1292, D1291, D1280, D1289, D1287, D1290, D1286,D1284, and D1282, respectively. The inputs of these delay oircuits areconnected to receive the outputs, respectively, of amplifiers A1293,A1292, A1291, A1280, A1289, A1287, A1290, A1286, A1284, and A1282. Theinputs to these amplifiers last mentioned are designated, respectively,as set R001 lead, set R002 lead7 set R003 lead, the set RS lead, the setRI lead, the set ROM lead, the set RO lead, set RN lead, the set RDlead, and the set IC lead. The output of the amplifiers A1293, A1292,A1291, A1280, A1289, A1287, A1290, A1286, A1284, and A1282 are appliedthrough a series of or circuits to an amplifier A1299, the output ofwhich is applied to reset terminals R of each of the v-arious statuslevel control fiip-fiops 47. Each of the set leads is activated byrecognition circuits. Thus a three-input and gate 1278 is providedhaving its output applied to the set R001 lead. One input to the gate1278 is from the status level IC. The status level IC is assumed highupon the completion of any given instruction. The same occurs at theendv of the operation M as will be subsequently discribed. The secondinput to the gate 1278 may, for the purposes of this invention, beconsidered always high. The third input to thegate 1278 is from theeighth delayed timing pulse TSa.

A second rtwo-input ga-te 1300 is connected through an or circuit alongwith the output of the gate 1278 to the set R001 lead. The gate 1300receives one input from the eighth delayed timing pulse Ta. The secondinput to the gate 1300 is indicated by a designation start which, mayfor example, -be the start push button whereby the computer is firststarted into operation, and the status level R001 is first to beselected.

A two-inp-ut gate 1280 has one input from a status level R001, and asecond input from the eighth delayed timing pulse Ta. The output ofthegate 1280 is applied to the set R002 lead. Similarly, a two-input gate1275 receives one input from the status level R002 and a second inputfrom the eighth delayed timing pulse TSH, The o-utput of the gate 1275is applied to the set R003 18 lead. A three-input gate 1234 is employedto provide an output to the set RS lead. The first of the three inputsto the gate 1234 is provided by the operation level M. The second andthird inputs, respectively, to the gate 1234 are received from thestatus level R003 and the eighth delayed timing Ypulse T8a.

Four gates 1249, 1250, 1251 and 1252 respectively, are coupled throughor circuits to the set RI lead. The rst of these gates namely, gate 1249is a three-input gate. The first of the three inputs is provided by theoperation level M. Remaining two inputs are provided by the status levelRO, and the eighth delayed timing pulse T8a. The second gate 1250 isalso a three-input gate receiving inputs from the operation level M, thestatus level RD, and the eighth delayed timing pulse T8a. Another ofthese group of four gates 1251 is a five-input gate. The first two ofthese inputs are received from the status level ROM and the eighthdelayed timing pulse T8a, respectively. Third input tothe gate 1251 isprovided by the not SPR output from the recognition gate R1052 (FIG. 4).The fourth input -to the gate 1251 is provided by the not ISSR outputfrom the recognition circuit R1054 (FIG. 4). The final input tothe gate1251 is received from the Zero output of the been-in RN flip-iiop F1111(FIG. 5). The last of these four gates, namely gate 1252, is aseven-input gate receiving inputs from the operation level M, the statuslevel RS, and the eighth delayed timing pulse T8a. An additional two ofthe seven inputs are received frcm the not SPR and the not SPLrecognition circuits R10-52 and R923 (FIG. 4), respeotively. The finaltwo inputs to the seven-input gate 1252 received from the not ISSR-andnot ISSL recognition gates R1054 and R922 (FIG. 4), respectively.

The set ROM lead is connectedto receive the outputs of an or circuitwhich in turn receives inputs from either of -two gates 1239 or 1240,respectively. The first of these gates 1239 is a live-input gatereceiving three of the inputs from the operation level M, the stauslevel RI, and the eighth delayed timing pulse T8a. The remaining twoinputs to the gate 1239 are provided by the one output of the 2 stage ofthe nines counter 45 (FIG. 5), and the one output of the 23 stage of thenines counter 45 (FIG. 5). The remaining gate 1240 connected to the setROM lead is a four-input gate receiving inputs freni the status levelRN, and the eighth delayed ltiming pulse T8a. The iinal two inputs tothe gate 1240 are provided by the one outputs of the 20 and 23 stages ofthe nines counter 45 (FIG. 5) as set forth above. Y

The output of three gates 1265, 1266, and 1271 are connected through orcircuits to the set RO lead. The first of these three gates, namely gate1265, is a four-input gate receiving inputs from the status level ROM,and the eighth delayed timing pulse T8a. The remaining two inputs to thegate 1265 are received from the nines counter not nine outp-ut (FIG. 5)and fro-m the one output of the been-in RN flip-flop F1111 (FIG. 5 Thesecond gate 1266 is a three-input gate. First input to the gate 1266 isprovided by the status level RN. The second input to the gate 1266 isfrom the eighth delayed timing pulse T8a. A nal input to the gate 1266is provided by the nines counter not n-ine output (FIG. S). The finalone of the three gates, namely gate 1271 is a five-input gate. Three ofthe inputs to the gate 1271 are provided by the operation level M, thestatus level RI, and the eighth delayed timing pulse TSa. The fourthinput to the gate 1271 is provided by the nines counter not nine output(FIG. 5 The final input is provided by the Zero output of the EOBOflip-flop F1110 (FiG. 5).

The output of a single gate 1237 is connected to the set RN lead. Fourpriming inputs to the gate 1237 are provided, the first of which beingfrom the operation levell M. The second and third input to the gate 1237are from the status level RI, and the eighth delayed timing pulse 19T8a. The final input to the gate 1237 is provided by the one output ofthe EOBO ilip-op F1110 (FIG.

The output of a seven-input gate 1224 is connected to the set RD lead.Two of Ithe inputs to gate 1224 are from the status level ROM and theeighth delayed timing pulse T8a, respectively. An additional two inputsto the gate 1224 are provided by the one outputs of the respective 2 and23 stages of the nines counter 45 (FIG. 5). The one output of thebeen-in RN Hip-flop F1111 (FIG. 5) provides an additional input to thegate 1224. The iinal two inputs to this gate are received from the notISSR and not SPR outputs olf the recognition gates R10'54 and R1052(FIG. 4), respectively.

Finally, the input to the set IC lead is received from the output of anor circuit receiving inputs from either of two gates 1206 or 1207. Threeof the inputs to the gate 1206 are provided by the operation level M,the status level ROM, and the eighth delayed timing pulse TSa. Remaininginput to the gate 1206 is received from the output of an or circuit,which in turn, receives inputs from either the SPR or ISSR leads (FIG.4). Similarly, the gate 1207 receives inputs from the operation level M,the status level RS, and the eighth delayed timing pulse TSa. The fourthand nal input to the gate 1207 is provided by the output of an orcircuit receiving inputs from either the ISSR or ISSL leads of FIGURE 4.The specific operation of these circuits of FIGURE 6 will be describedin detai1 in Section 3.1 below.

3.0 Operation 3.1 Statczing instructions The instructions to becompleted may be stored in a surge tank section of the left and rightHSM and 16 as described, for example, in the patent to Bensky et al.,2,679,268. Thus it may be assumed that a preceding instructionwithrlrawn from the HSM 15, 16 has been performed by the machine andthat the current instruction to multiply two numbers (operation M) isnow to be withdrawn from the surge tank. In this event, the status levelIC is presumed to be high along with ano-ther input (herein labeledhigh) to the status transition gate 1278 (FIG. 6). Therefore gate 1278passes the eighth delayed timing pulse T851 to the set R001 lead.

In the alternative, for simplicity of description, it might be assumedthat the sole function of the machine is to multiply two numbers, inwhich event, a gate 1300 may be utilized. In this event, a start signalprovided by the operator will prime the gate 1300, which, upon theoccurrence of the eighth delayed timing pulse TSa, sets the set R001lead. The pulse thus passed, in either of these two cases, is amplifiedby the amplifier A1293 and A1299. Pulse passed by the ampliiier A1299resets al1 of the status level control flip-flops 47. After passingthrough the delay circuit D120?, the pulse sets the status level controlliip-liop F1293 and the status level R001 is high.

3.1.1 Status level R001 high Having just provided a start signal, andthe R001 status level having been selected, the gate 502 (FIG. 2) passesthe first timing pulse T1 to reset the A and B counters 10 and 11,respectively (FIG. 2). Simultaneously therewith, gate 629 (FIG. 1)passes the first timing pulse to prime gates 630 and 630a (FIG. 1).Gates 630 and 63011 thus primed allow the program subcounter PSC toaddress the left and right HSM I15 and 16 (FIG. 3), respectively, at(000), the location of the fourteen (14) most significant bits of thelirst instruction. It may be assumed that the program subcounter PSC(FIG. 1) has a count corresponding to the address in the memorycorresponding to the instruction (to perform operation M- multiply)about to be read out. Also gate 1401 (FIG. 1) passes the first timingpulse T1 thereby resetting the 0 register 30 (FIG. l).

During the second timing pulse T2 the gate 244 (FIG. 1) increases thecount of the program subcounter PSC by one. Second timing pulse T2 alsopasses through the gate 481 (FIG. 2) thereby resetting the A register26. Note that the gates 630 and 63011 (FIG. l) were closed before theprogram subcounter PSC count was advanced.

The leift and right read-out gates 730 and 862, respectively (FIG. 3),have high outputs because of the high status level R001 which activatesthe read-out circuits of the left and right HSM 15 and 16 (FIG. 3),respectively. The information to be read out of the left HSM 15 and theright HSM 16 (FIG. 3) thus becomes avail* able during the tth and sixthtiming pulses T5-T6 from the location addressed during the immediatelypreceding iirst timing pulse T1. The six bits from the output of theleft HSM 15 (FIG. 3) are now passed through the gates 1402 to the 0register 30 (FIG. l). Simultaneously the sixth timing pulse T6 opens thegate 402 (FIG. 2) whereupon the six bits from the right HSM 16 (FIG. 3)are passed to the six highest order stages of the A register 26 (FIG.2). Since the 0 register 30 (FIG. 1) receives the six bits applied toit, which are here assumed to be co-ded for the operation matrix OM(FIG. l) to select the operation level M, the operation M is selectedand becomes high, all other operation levels remaining low.

TSa

The status transition gate 1280 (FIG. 6) passes the eighth delayedtiming pulse T8Q to the set R002 lead, in a manner similar to that whichthe R001 status level was selected to be high. The status level R002 isnow selected to be high. Because of the similarity in the manner inwhich the different status levels are selected, i.e., passing of theeighth delayed timing pulse T811 to an appropriate set lead followed byresetting all the status level control flip-flops 47, and thereafterapplying the delayed pulse from the appropriate set lead to theappropriate one of the status level control iip-ops 47 to set theselected i-lip-iiop and cause the selected status level to be high, nofurther description of this selection is believed necessary. Further itis believed unnecessary to describe in detail the selection of thestatus levels. The status level R002 is now high.

3.1.2 Status level R002 high During R002 the second third of theinstruction is transferred from the HSM to the several registers andcounters.

The -gates 630 and 630e (FIG. 1) are again opened by the rst timingpulse T1 passed through the gate 629 (FIG. l). The address circuits ofthe left and right HSM 15 and 16 respectively (FIG. 3) are thusaddressed by the program subcounter PSC through the gates 630 and 630a(FIG. 1).

The count of program subcounter PSC (FIG. 1) is advanced by one asbefore. The program subcounter PSC now holds the address of the HSMlocation of the last third of the instruction multiply.

The read out circuits of the left and right HSM 15, 16 (FIG. 3)respectively are activated by the left and right read out gates 630 and362 respectively (FIG. 3) as previously described. At the sixth timingpulse T6 the ,gates 405 (FIG. 2) are opened to iill the remaining threelow order bits of the A register 26 from the left HSM 15 output. At thesame time, the gate 512 (FIG.

2) passes the sixth timing pulse T6 to open the gates Y21 544 (FIG..2)thereby passing the other three bits from the left HSM (FIG. 3) into theB counter 11 (FIG. 2) and six bits from the right HSM 16 (FIG. 3) to thegates 547 (FIG. 2) and into the B counter 11. Note v that in thisinstance, the B counter acts the same as the register.

Status transition gate 1245 (FIG. 6) passes the eighth delayed timingpulse T8Q to cause-the status level R003 to be high. l

3.1.3 Status level R003 high During status level R003, the final thirdof the instruction is transferred from the HSM into the severalregisters.Y

' AS in anciana R002, gate 629 (F1o. 1) primes gat-es' 630 and 63011thereby addressing the HSM 15, 16 at the addresses previously set intothe program subcounter PSC (FIG. l).

The count of the program subco-unter PSC (FIG. l) is advanced by one asbefore. C register 28 (FIG. 2) is reset by the gate 442 (FIG. 2) whichpasses the second timing pulse T2 to perform the resetting operation.

The contents of the A Aregister (FIG. 2) are transferred through gate541 to the A counter 10 (FIG. 2). Gate 510 passes the fourth timingpulse T4 to open the gate 514. f

' TS-Te The left and right read-out gates 730 and 362 respectively (FIG.3) are opened and their outputs have a high level there-by activatingthe read-out circuits of the left I operation to be performed isselected.

and right HSM 15, -16 (FIG.'3) as occurred in the preceding status levelR001 and R002. The sixth bits from the left HSM S15 (FIG. 3) passthrough the gate 436 (FIG. 2) and are entered into the six higher orderstages of the C register 2S (FIG. 2). At the sameA time the three lowestorders of these six bits-also pass through l the -gate 324 (FIG. 2) andare entered in the three higher order stages of the C counter 12.-Simultaneously Vthe six bits Yfrom the right HSM 16 (FIG. 3) passthrough the gate 430 (FIG. 2) which were primed during the sixth timingpulse T6 into the six lowest order stages of the C register 28 (FIG. 2).These same six bits from the right HSM 16 (FIG. 3) also simultaneouslypass through the gates 318 to the six lowestporder stages of the Ccounter 12 (FIG. 2). Accordingly the l2 bits, six from the left HSM 15and six from the right HSM 16, are now entered in the C register 28. Thenine lowest ordered ones of these bits are also entered in the C counter12.

By way of information thethree highest order bits 29,

21, and 211 are-entered in the C register from the left HSM 15 (FIG3)for certain further usages which will The gate 239 (FIG. l) passes theseventh timing pulse T7 to reset the'program subcounter PSC.

Upon the advent of the eighth delayed timing pulse T8Q, the statustransition gate 1234 (FIG. 6) selects the status level RS.

events in which the instruction is taken from the high speed memory andplaced in a group of flip-flop registers and counters. From theregisters and counters it is then possible to set up conditions for anoperationto address the high speed memory at the location of the datarequired to perform the operation and'to address the high speed memoryat the location where the answer, if any, is to be stored, v Theinstruction has been stored inthe high speed memory either during aprevious surge olf instructions from the program drum in the surge tanksin both halves of the high speed memory or by a manual setting" by anoperator. Therefore, Vthree status levels memory. The status levels thatwill be activated during the staticizing of an instructionare termedR001, R002,

and R003. One-third of the instruction is staticized during each of4these levels.

In R001, a portion of the rst third of the instruction is stored in the0 register 30 (FIG. l), from which the In addition, a portion of thefirst third of the instruction is stored in the A register (FIG. 2).

During R002, the second third of the instruction is staticized. Thus thestorage in the A register 26 (FIG. 2) is completed and storage in the Bcounter 11 (FIG. 2) is performed. v

During R003, the last third of the instruction is staticized in the Cregister 28 (FIG. 2). Simultaneously the least significant nine bits ofthis groupwhich were transferred to theC register are transferred to theC counter 12 (FIG. 2). Also during R003, the contents of the A registerare transferred to the A counter. Particular usage of the instruction asstaticized will be illustrated in the succeeding section 3.2, relatingto perfor-ming of specic operations of multiplication.

3.2 Performing operation M (multiplication) n To perform multiplicationthe multiply instruction is staticized in the usual way and arranged asfollows:

0 section Code number for multiplication. A section Address of themultiplicand. B section Address of the multiplier. C section Address ofthe product.

Upon the occurrence of the eighth -delayed timing pulse Ta, the statuslevel RS is selectedvia by thestatus transition gate 1234 (FIG. 6) which-is now primed by the high operation level M. As described above, theoutput ofv gate 1234 actuates amplifier A1280 which in turn provides anoutput through delay line D1280 of the status'level control flip-dopF1280 whereupon the status level RS comes high. v

Note that under this state of conditions the space-left flip-flop F911(FIG. 4) is in the set condition. The'set condition in the space-leftflip-flop F911 results from the passage of the rst timing pulse T1through the gaie 945, during the high status level R003, to the setinput of thespace-left dip-flop. VAlso the space-right flip-Hop F10-03(FIG. 4) is in the set condition having received shifts, no negativeoperands being permitted. The firstl phase of the operation is a searchfor the least significant digits of (l) the multiplicand, located in theleft HSM 15 and addressed by the ,A counter 10, and (2) of themultiplier located in the right HSM 16 and addressed by acreage the Bcounter 11. This searching entails reading out of the addressed memorylocations into .the Y and Z registers 13 and 14 from which recognitionby the symbol recognition circuits 22, 23 takes places. The leastsignificant multiplier digit is then read through the nines complementer21 to the nines counter 45. Thereby, the nines counter is preset withthe nines complement of the multiplier digit.

When both of these least significant digits have been located, the firstseries of additions in the duplicated binary adder and binary codeddecimal converter 17 is begun. The multiplicand is added to the partialproduct (normally zero at the start), which is located in the right HSM16 and addressed by the C counter12, by means of successive cycles ofread out and read in until the item separation symbols are recognized,The resulting sum is read back into the ypartial product location in theright high speed memory as addressed by the C counter 12. When the endof the multiplicand is recognized, the count of the nines counter 45 isincreased by one and a check is made for overflow (when the ninescounter reaches nine). If no overflow has occurred, a further additionis necessary. However, the A and C counters and 12, have been increasedduring the previous addition and it is now necessary to reset them totheir original addresses. This address information is retained by the Aand C registers 26 and 28 which restore the A and C counters 10 and 12,respectively, to the least significant digit addresses of the partialproduct and multiplicand. When the nines counter overflows a newmultiplier digit is read from the right HSM 16 through the ninescomplementer 21 into the nines counter 45. An effective shift of thepartial product is now made by increasing by one the address of theleast significant digit of the partial product and setting the Cregister 2S and C counter 12 with this information. A new series ofadditions is now performed until the nines counter again overiiows.

Upon this overiiow a shift is again made and another series of additionsbegun. This process of adding until the nines counter 45 overiiows,shifting, and adding again, proceeds until an item separator symbol isrecognized bythe symbol recognition circuits 22 during the multiplierread out. Upon such recognition, the operation is terminated. Theproduct will now be found in the HSM with the least significant digit atthe C address of the original multiplication instruction. Note here, theuse of the registers to back up the counters, so that a search for theleast significant digits of the operands need be made only once. Notealso the unique shifting arrangement wherein the address only of thepartial product is shifted and not the entire partial product itself.Both of these features provide for a novel high speed operation uponvariable non-standard maximum length items. Having thus described themultiply operation in general, the

operation will now be described in detail following the sequences ofstatus levels and timing pulses.

322.1 Status level RS high During staticizing yas described above, theaddress of the multiplicand is staticized in the A register 26 andsubsequently transferred to the A counter 10 (FIG. 2). Similarly theaddress of the multiplier is read (staticized) directly into the Bcounter 11 (FIG. 2). Finally the address of the product is staticized inthe C register 2S (FIG. 2) and into the C counter 12. Under theseconditions, with the operation level M and the status level RS high, theA counter 10 addresses the multiplicand location in the left HSM (FIG.3) through the gates 640 by a simple transfer of the contents of the Acounter to the addressing circuits of the left HSM 15. Similarly the Bcounter 11 (FIG. 2) addresses the right HSM 16 (FIG. 3) through thegates 670. The gates 670` (FIG.

2) are primed by the output of the gate `693. Both gates 670 and gates69:3 (FIG. 3) pass the first timing pulse T1 to provide this priminginput. Simultaneously the A register 26 (FIG. 2) is cleared by thisfirst timing pulse T1 which is passed through the gate 404, theremaining inputs to the gate 404 being primed by the RS status level andthe one output of the space-left fiip-op F911 (FIG. 4), which wasdescribed before as being high during the status level RS.

During the second timing pulse T2 the gates 414 (FIG. 2), primed by thespace-left flip-flop F911 (FIG. 4) one output, pass the contents of theA counter 10 (FIG. 2) into the A register 26 (FIG. 2). Simultaneouslythe gate 508 primed by the one output of the space-right iiipiiop F1008(FEG. 4) passes the second timing pulse to advance the count of the Bcounter 11 (FIG. 2) by one At the third timing pulse T3 the count of theA counter 10 (FIG. 2) is advanced by one by a pulse from the gate 505.By this advance of the A and B counters 10 and 11, respectively, thesuccessive least significant digits are read out during each RS cyclefrom the .two memory banks until a non-space character is encountered inboth locations.

The nines counter 45 (FIG. 5) has four Hip-flop stages and is so termedbecause it is used to count up to nine starting from the complement ofeach multiplier digit. The nines counter 45 in this case is reset by thefourth timing pulse T4, passed through the gate G1 (FIG. 5) which isprimed by the output of the one terminal of the space-right fiip-iiopF1008 (FIG. 4). This priming occurs preparatory to the entry of thecomplement of the multiplier digit during the succeeding sixth andseventh timing pulses FI`6-T7. Inother Words, if a space is notrecorded'in the Z register 14, the gate 902, being primed by the oneoutput of the space-left flip-flop F911 (FIG. 4), passes the fourth-timing pulse to reset the Y register 13 (FIG. 4). The Z register 14 issimilarly reset by the fourth timing pulse T4 which in turn is passedthrough the gate 1042 and thence through the delay circuit D56. The gate1042 receives its priming input from the one output of the space-rightfiip-iiop F1008 (FIG. 4). Note that with the status level RS high andthe operation level M high, the left and right read-out gates 730 and862 (FIG. 3), respectively, apply a high level to activate the read-outcircuits of the left and right HSM 15 and 16 (FIG. 3), respectively.Accordingly, the left and right HSM 15 and 16 are conditioned forreading out information.

With the occurrence of thesixth timing pulse T6 the contents of theleftHSM 15 (FIG. 3) at the location addressed during the first timing pulseT1 from the A counter 10 (FIG. 2)'are now passed through the gates 911`(FIG. 4) into the Y register 13. Gates 911 are primed by the output ofgate 918 which is primed by the RS status level and the one output ofthe space-left flip-fiop F911 (FIG. 4). Similarly the contents of theright HSM 16 (FIG. 3), as addressed by the B counter 11 (FIG. 2), passinto the Z register 14 (FIG. 4) through the gates 1032 (FIG. 4). Gates1032 are opened, that is primed, by the sixth timing pulse T6 from thegate 1031. Gate 1031 receives inputs from the RS status level, the sixthtiming pulse T6, and the one output of the space-right v Hip-flop F1008.The remaining input to the gate 1031 may be described, for the purposesof this invention as continuously high.

With the occurrence of an enlarged timing pulse T6- T7 the gate G13applies a high level to the nines comple-

